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Piet De Moor (IMEC)

“Backside illuminated imager developed at imec”

Title: Imager technologies for high speed applications
Author: P. De Moor, Maarten Rosmeulen, Luc Haspeslagh, Paul Goetschalckx, Stefano Guerrieri and Jonathan Borremans
Affiliation: IMEC, Leuven, Belgium
Email: Piet.DeMoor[at]imec.be
URL: http://www.imec.be
Abstract:
Backside illuminated imager developed at imec
For demanding imaging applications such as very high speed imaging, standard CMOS imager technologies are not optimally suited.  By nature, when operating an imager at very fast frame rates, the number of photons collected per frame is low.  Hence a maximal intrinsic pixel sensitivity is required.  This can be achieved by using backside illuminated imagers as their fill factor is 100%.  Once the photo-carriers are created inside the imager, one has to minimize the collection time.  This can be achieved by engineering the thickness and doping of the epitaxial Si substrate.  From the moment the charges are collected in the pixel, one has to read out them as fast as possible.  In order to not be limited by the electronic read-out time, burst-type of imaging can be done by storing multiple frames inside the pixel (and reading them out at a later stage).  While storage in voltage domain comes with a noise penalty, analog (charge) type of storage is in interesting alternative.  However, fast readout of a 2D array benefits from the use of power efficient and high-speed CMOS circuits.  The embedded CCD-in-CMOS (eCCD) technology allows the combination of both.  Finally, if continuous imaging at very high speed is required, a vertical parallel readout is required using 3D stacking of imager and readout circuits.  In this paper, imec’s technology solutions for backside illumination, dedicated epitaxial substrates, eCCD technology and 3D stacking will be discussed.
Biographical Sketch: Piet De Moor is Program Manager image at imec. He has received his PhD in Physics from University of Leuven in 1995. He joined imec in 1998 and was involved in the development of different process technologies and devices including MEMS bolometers, 3D wafer stacking, backside illuminated imagers and embedded CCD-in-CMOS imagers.  He has been technically coordinating several bilateral, EC, ESA, and nationally funded projects.

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